Joe Ganley

Résumé

Summary:

I am a software architect, developer, and manager with a 15+-year track record of successfully delivered software. I am an expert C++ programmer, am proficient in Python and Lisp, and have experience in many other languages and technologies as well.

I specialize in solving hard problems, such as manipulating enormous volumes of data and optimization algorithms for NP-hard problems.

Presently I manage a suite of data-analytics software. I am responsible for all aspects of its software development, project management, QA, documentation, configuration management, and release logistics. I am also active in the actual programming of the product.

I have a Ph.D. in Computer Science and I have received 22 patents for algorithmic innovations.

Skills:
Languages: C++, C, Python, Lisp/Scheme, Skill, Java, familiar with many more.
Platforms: Windows/Visual C++, many flavors of Unix, OpenGL, Qt, COM, .NET.
Particular subject strengths: Algorithms, data structures, compilers, graphics, user interface design.

Work Experience:
Senior Computer Scientist, 2008 to Present
White Oak Technologies, Inc., Silver Spring, Maryland
    I am the general manager as well as an active software developer for a suite of data-analytics software. Previously I worked on other analytics and visualization tools to help users make sense of enormous volumes of data.
Staff R&D Engineer, 2006 to 2008
Synopsys, Inc., Vienna, Virginia and Mountain View, California
    I worked on an entirely new suite of interactive graphical software for integrated circuit design automation. This suite includes applications development and usability challenges as well as algorithmically difficult problems. My position was that of software architect, fully responsible for a large portion of the applications infrastructure of this suite of software. My responsibilities included writing functional and implementation specifications, project management, implementation (in C++ and Tcl), as well as managing a team of developers overseas who contributed to the code that I owned. The development platform was C++ on Linux. [Data sheets for products in this suite: Layout Editor, Schematic Editor, and Schematic_Driven Layout.]
Senior Member of Consulting Staff, 2003 to 2006
Cadence Design Systems, Vienna, Virginia and San Jose, California
    I worked on OpenAccess, which is an open-source, state-of-the-art EDA database package, and on associated infrastructure code. The development platform was Microsoft Visual Studio .NET, and the target platforms also included a variety of Unix flavors.
Senior Member of Consulting Staff, 2002 to 2003
Cadence Design Systems, Vienna, Virginia and San Jose, California
    I rejoined Cadence when they acquired Simplex. My duties were the same as at Simplex, plus working with other Cadence teams to interface their tools with Simplex's X Architecture toolset, and to retrofit their tools with awareness of the particular challenges of optimizing for the X Architecture.
Senior Engineering Manager, 2002
Senior Staff Engineer, 2000 to 2002
Staff Engineer, 1999 to 2000
Simplex Solutions, Inc., Vienna, Virginia and Sunnyvale, California
    I designed and implemented a world-class placement system for the X Architecture, a new integrated-circuit architecture we devised at Simplex that features extensive use of diagonal interconnect. The purpose of the placement tool is to generate, from a circuit netlist, a physical location for each component that meets aggressive goals with respect to wirelength, routing congestion, and timing under the X Architecture. I have received twenty patents for this work. The development platform was Visual C++ under Windows NT, and the target platforms also included Linux and a variety of other flavors of Unix. I was the second employee on the X Architecture project, so I also wrote a great deal of associated infrastructure such as databases and input/output parsing. Using the code that I wrote, we successfully completed a number of benchmarks in order to gain customer acceptance of the X Architecture. As a manager, I supervised a placement team consisting of myself and two direct reports, and was the lead architect of the X Architecture placement strategy.
Member of Consulting Staff, 1996 to 1999
Senior Member of Technical Staff, 1995 to 1996
Cadence Design Systems, San Jose, California (from late 1996 on, full-time teleworker from Virginia)
    I rewrote the core layout generation code of the Virtuoso-XL product to improve performance, maintainability, and extensibility. The purpose of this code is to generate, from a schematic, a functionally equivalent physical layout and to maintain the correspondence between the schematic and the layout during editing of each. I was the project leader, principal designer, and primary developer of the Device-Level Placer (DLP) product. I received a patent for part of the DLP technology. Duties included software architecture and design, writing functional and implementation specifications, implementation (in C under Unix/Motif), and supervising other developers' contributions. I also designed and developed new features and provided maintenance support for many of Cadence's existing electronic CAD software products. [Screenshot, Virtuoso XL datasheet, and Virtuoso datasheet.]

Education:
Ph.D. in Computer Science
University of Virginia, Charlottesville, Virginia
May 1995
Dissertation: Geometric Interconnection and Placement Algorithms
Advisor: James P. Cohoon

M.S. in Computer Science
Virginia Tech, Blacksburg, Virginia
August 1992
Thesis: Heuristics for Laying Out Information Graphs
Advisor: Lenwood S. Heath

B.S. in Computer Science
Virginia Tech, Blacksburg, Virginia
July 1990

Honors:
"Armchair Marketing Award" from Simplex for coining the term "liquid routing," 2002
Simplex Values Award, 1999
Nominated for Cadence Quality Award, 1998
Cadence Quality Award, 1997
Cadence Engineering Special Achievement Award, 1995
Nominated for ACM Doctoral Dissertation Award, 1995
Nominated for DiPrima (SIAM Doctoral Dissertation) Prize, 1995
Virginia Space Grant Fellowship, 1994
University of Virginia Dean's Fellowship, 1992-93
Member of Tau Beta Pi Engineering Honor Society, since 1992

Patents:
  1. U.S. Patent 7,398,498, Method and apparatus for storing routes for groups of related net configurations, issued 8 July 2008.
  2. U.S. Patent 7,143,382, Method and apparatus for storing routes , issued 28 November 2006.
  3. U.S. Patent 7,139,994, Method and apparatus for pre-computing routes , issued 21 November 2006.
  4. U.S. Patent 7,100,137, Method and apparatus for quantifying the quality of placement configurations in a partitioned region of an integrated circuit layout , issued 29 August 2006.
  5. U.S. Patent 7,089,523, Method and apparatus for using connection graphs with potential diagonal edges to model interconnect topologies during placement, issued 8 August 2006.
  6. U.S. Patent 7,080,336, Method and apparatus for computing placement costs, issued 18 July 2006.
  7. U.S. Patent 7,055,120, Method and apparatus for placing circuit modules, issued 30 May 2006.
  8. U.S. Patent 7,024,650, Method and apparatus for considering diagonal wiring in placement, issued 4 April 2006.
  9. U.S. Patent 6,988,256, Method and apparatus for pre-computing and using multiple placement cost attributes to quantify the quality of a placement configuration within a partitioned region, issued 17 January 2006.
  10. U.S. Patent 6,910,198, Method and apparatus for pre-computing and using placement costs within a partitioned region for multiple wiring models, issued 21 June 2005.
  11. U.S. Patent 6,907,593, Method and apparatus for pre-computing attributes of routes, issued 14 June 2005.
  12. U.S. Patent 6,904,580, Method and apparatus for pre-computing placement costs, issued 7 June 2005.
  13. U.S. Patent 6,848,091, Partitioning placement method and apparatus, issued 25 January 2005.
  14. U.S. Patent 6,826,737, Recursive partitioning placement method and apparatus, issued 30 November 2004.
  15. U.S. Patent 6,802,049, Method and apparatus for computing placement costs by calculating bend values of connection graphs that model interconnect line topologies, issued 5 October 2004.
  16. U.S. Patent 6,795,958, Method and apparatus for generating routes for groups of related node configurations, issued 21 September 2004.
  17. U.S. Patent 6,687,893, Method and apparatus for pre-computing routes for multiple wiring models, issued 3 February 2004.
  18. U.S. Patent 6,678,872, Method and apparatus for using a diagonal line to measure congestion in a region of an integrated-circuit layout, issued 13 January 2004.
  19. U.S. Patent 6,671,864, Method and apparatus for using a diagonal line to measure an attribute of a bounding box of a net, issued 30 December 2003.
  20. U.S. Patent 6,651,233, Method and apparatus for measuring congestion in a partitioned region, issued 18 November 2003.
  21. U.S. Patent 6,516,455, Partitioning placement method using diagonal cutlines, issued 4 February 2003.
  22. U.S. Patent 6,161,078, Efficient method for solving systems of discrete rotation and reflection constraints, issued 12 December 2000.

Publications:
    Book Chapters

  1. J. Frankle, A. Fujimura, J. L. Ganley, A. Hetzel, and S. Teig, The X Architecture, invited chapter contribution in Handbook of Algorithms for Physical Design, C. J. Alpert, D. P. Mehta, and S. S. Sapatnekar, editors, Auerbach, 2008. (front page)
  2. J. P. Cohoon and J. L. Ganley, Rectilinear Interconnections in the Presence of Obstacles, invited chapter contribution in Advanced Routing of Electronic Modules, M. Pecht and Y. T. Wong, editors, CRC Press, Boca Raton, FL, 1996.

    Journal Publications

  3. J. L. Ganley and L. S. Heath, The pagenumber of k-trees is O(k), Discrete Applied Mathematics 109 (2001) 215-221.
  4. I. I. Mandoiu, V. V. Vazirani , and J. L. Ganley, A new heuristic for rectilinear Steiner trees, IEEE Transactions on Computer-Aided Design 19 (2000) 1129-1139.
  5. J. L. Ganley, Computing optimal rectilinear Steiner trees: A survey and experimental evaluation, Discrete Applied Mathematics 89 (1999) 161-171. (Special issue on combinatorial methods in VLSI design.)
  6. J. L. Ganley and J. S. Salowe, The power-p Steiner tree problem, Nordic Journal of Computing 5 (1998) 115-127.
  7. M. J. Alexander, J. P. Cohoon, J. L. Ganley, and G. Robins, Placement and routing for performance-driven FPGAs, VLSI Design 7 (1998) 97-110.
  8. T. Carpenter, S. Cosares, J. L. Ganley, and I. Saniee, A simple approximation algorithm for two problems in circuit design, IEEE Transactions on Computers 47 (1998) 1310-1312.
  9. J. L. Ganley and J. P. Cohoon, Provably good moat routing, Integration: The VLSI Journal 27 (1998) 47-56.
  10. J. L. Ganley and L. S. Heath, An experimental evaluation of local search heuristics for graph partitioning, Computing 60 (1998) 121-132.
  11. J. L. Ganley, Accuracy and fidelity of fast net length estimates, Integration: The VLSI Journal 23 (1997) 151-155.
  12. J. L. Ganley and J. P. Cohoon, Minimum-congestion hypergraph embedding in a cycle, IEEE Transactions on Computers 46 (1997) 600-602.
  13. J. L. Ganley and J. P. Cohoon, Improved computation of optimal rectilinear Steiner minimal trees, International Journal of Computational Geometry and Applications 7 (1996) 457-472.
  14. J. L. Ganley and J. S. Salowe, Optimal and approximate bottleneck Steiner trees, Operations Research Letters 19 (1996) 217-224.
  15. J. L. Ganley and J. P. Cohoon, Rectilinear Steiner trees on a checkerboard, ACM Transactions on Design Automation of Electronic Systems 1 (1996) 512-522.
  16. J. L. Ganley and L. S. Heath, Heuristics for laying out information graphs, Computing 52 (1994) 389-405.
  17. J. L. Ganley and L. S. Heath, Optimal and random partitions of random graphs, The Computer Journal 37 (1994) 641-643.

    Conference Publications

  18. I. I. Mandoiu, V. V. Vazirani , and J. L. Ganley, A new heuristic for rectilinear Steiner trees, in Proceedings of the International Conference on Computer-Aided Design, pages 157-162, 1999.
  19. J. L. Ganley, Efficient solution of systems of orientation constraints, Proceedings of the International Symposium on Physical Design, 1999.
  20. I. I. Mandoiu, V. V. Vazirani, and J. L. Ganley, A new heuristic for rectilinear Steiner trees, in Proceedings of the Conference on Advanced Research in VLSI, 1999.
  21. E. Malavasi, J. L. Ganley, and E. Charbon, Quick placement with geometric constraints, in Proceedings of the Custom Integrated Circuits Conference, pages 561-564, 1997.
  22. J. L. Ganley and J. P. Cohoon, A provably good moat routing algorithm, in Proceedings of the Sixth Great Lakes Symposium on VLSI, pages 86-91, 1996.
  23. J. L. Ganley and J. P. Cohoon, Thumbnail rectilinear Steiner trees, in Proceedings of the Fifth Great Lakes Symposium on VLSI, pages 46-49, 1995.
  24. J. L. Ganley, M. J. Golin, and J. S. Salowe, The multi-weighted spanning tree problem, in Proceedings of the First International Computing and Combinatorics Conference, pages 141-150, 1995.
  25. M. J. Alexander, J. P. Cohoon, J. L. Ganley, and G. Robins, Performance-oriented placement and routing for field-programmable gate arrays, in Proceedings of the European Design Automation Conference, pages 80-85, 1995.
  26. M. J. Alexander, J. P. Cohoon, J. L. Ganley, and G. Robins, An architecture-independent approach to FPGA routing based on multi-weighted graphs, in Proceedings of the European Design Automation Conference, pages 259-264, 1994.
  27. J. L. Ganley and J. P. Cohoon, Optimal rectilinear Steiner minimal trees in O(n2 2.62n) time, in Proceedings of the Sixth Canadian Conference on Computational Geometry, pages 308-313, 1994.
  28. J. L. Ganley and J. P. Cohoon, A faster dynamic programming algorithm for exact rectilinear Steiner minimal trees, in Proceedings of the Fourth Great Lakes Symposium on VLSI, pages 238-241, 1994.
  29. J. L. Ganley and J. P. Cohoon, Routing a multi-terminal critical net: Steiner tree construction in the presence of obstacles, in Proceedings of the International Symposium on Circuits and Systems, pages 113-116, 1994.

    Newspaper Article

  30. Joe Ganley, Click and Pick: A Window on the Web's 'Portal' Sites, The Washington Post, Business/Technology Section, 25 March 1999, page E6.

Activities:
Publicity Chair, Fifth ACM/SIGDA Physical Design Workshop, 1996
Member, SIGDA Outstanding Dissertation Committee, 1999.
Editor of "Theory Calendar" column for SIGACT News, 1994-95
Referee for numerous journal and conference articles
Co-chair of CS Graduate Student Group, University of Virginia, 1994-95
Vice President of CS Graduate Students, Virginia Tech, 1991-92
ACM Programming Team, Virginia Tech, 1989-91 (Placed 3rd in the world in 1991)
Virginia Tech ACM Chapter Secretary, 1990-91
Referee for numerous journal and conference articles, 1991-